1. Field of the Invention
The invention relates generally to semiconductor integrated circuit devices, and particularly, to a semiconductor integrated circuit device provided with an analogue signal processing circuit and a digital signal processing circuit on a single semiconductor substrate. The invention has particular applicability to voltage comparators.
2. Description of the Background Art
A large scale integrated circuit device comprises an analogue signal processing circuit (referred to as "analogue circuit" hereinafter and a digital signal processing circuit (referred to as "digital circuit" hereinafter), each formed on a single semiconductor substrate. For example, in an LSI with an A/D convertor, an analogue circuit which forms a comparator and a digital circuit which forms an encoder are provided.
Generally, a digital circuit is not easily influenced by noise, since it deals with a signal having binary values for signal processing. On the other hand, in an analogue circuit, the result of processing is frequently affected by noise, since it deals with a continuously changing analogue signal. Especially, noise generated from a digital circuit provided in a single semiconductor substrate is transmitted through the substrate to the analogue circuit, thereby often causing an adverse effect on processing in the analogue circuit.
FIG. 8 is a conceptional diagram of a conventional LSI. With reference to FIG. 8, the LSI1' comprises a CMOS analogue circuit 65 including CMOS transistors and a CMOS digital circuit 66 including CMOS transistors. Analogue circuit 65 receives an externally applied input voltage signal Vi, processes the signal and then applies a digital signal indicative of the result of processing to circuit 66. In digital circuit 66, digital signal processing is performed and a digital output signal Vo is output. As shown in FIG. 8, it is pointed out that in the conventional LSI1', analogue circuit 65 and digital circuit 66 are both formed of CMOS transistors.
As an example of CMOS analogue circuit 65 shown in FIG. 8, a voltage comparator is shown in FIG. 9. With reference to FIG. 9, the voltage comparator comprises input terminals 11 and 12 for receiving voltage signals V1 and V2, respectively, transmission gates SW1 and SW2 each connected to terminals 11 and 12, a capacitor Cc having one electrode connected to the outputs of transmission gates SW1 and SW2, an inverter 7 for receiving an output signal from capacitor Cc, a transmission gate SW3 connected between the input and the output of inverter 7, and an invertor 3 connected to the output of inverter 7. Inverter 3 outputs an output voltage signal V5 through an output terminal 15.
Each of transmission gates SW1, SW2 and SW3 is formed of PMOS transistors 22, 24, 26 and NMOS transistors 21, 23, 25, respectively. Transmission gates SW1 and SW3 are responsive to clock signals .phi. and .phi. generated from a clock generator (not shown) to be turned on during a first period, while transmission gate SW2 is turned off during the first period. Conversely, transmission gate SW1 and SW3 are responsive to clock signals .phi. and .phi. be turned off during a second period following the first period, while transmission gate SW2 is turned on during a second period. The backgate terminals of PMOS transistors 22, 24, 26, which constitute transmission gates SW1, SW2 and SW3, respectively are connected to a power supply V.sub.DD, and the backgate terminals of NMOS transistors 21, 23, 25 are grounded.
Inverter 7 comprises a PMOS transistor 47 and an NMOS transistor 41 connected in series between power supply V.sub.DD and ground. Transistors 41 and 47 are connected together with the other electrode of capacitor Cc at a node 14. Transistor 41 has its backgate terminal B.sub.N connected to ground, while transistor 47 has its backgate terminal B.sub.P connected to power supply V.sub.DD. Inverter 3 also comprises a PMOS transistor 16 and an NMOS transistor 17 connected in series between power supply V.sub.DD and ground.
Now, the voltage comparator shown in FIG. 9 will be described. During the first period, transmission gates SW1 and SW3 are turned on, while transmission gate SW2 is turned off. Therefore, an input voltage V1 is applied to one electrode (node 13) of capacitor Cc through transmission gate SW1. In addition, short circuit takes place between the input and the output of inverter 7 through transmission gate SW3, and the other electrode of capacitor Cc (node 14) is therefore brought to a prescribed intermediate potential V0.
The input-output characteristic of inverter 7 is shown in FIG. 10. That is, as represented by a curve IN in FIG. 10, inverter 7 is responsive to an input voltage V13 to output an output voltage V14. When inverter 7 is short-circuited between its input and output, the input voltage V13 and the output voltage V14 come on a straight line defined by equation V13=V14. Therefore, the intersection M between the straight line OL and the curve IN defines the intermediate potential V0. As a result, capacitor Cc stores a charge Q1 in accordance with the following equation. EQU Q1=Cc (V1--V0) (1)
During the second period following the first period, transmission gates SW1 and SW3 are turned off, and transmission gate SW2 is turned on. Accordingly, an input voltage V2 is applied to one electrode of capacitor Cc (node 13) through transmission gate SW2. Assuming that the input voltage V13 of invertor 7 is changed into a voltage V.sub.A because of this, capacitor Cc should have stored a charge Q2 in accordance with the following equation. EQU Q2=Cc (V2-V.sub.A) (2)
Since the charge Q1 equals the charge Q2, the following equation is obtained from equations (1) and (2). EQU V.sub.A -V0=V2-V1 (3)
Equation (3) indicates that the input voltage V13 of inverter 7 changes from the potential V0 to the potential V.sub.A, depending upon a change in voltage, i.e. V2-V1 applied to one electrode of capacitor Cc (node 13). The difference of the potentials V.sub.a -V0 is amplified in accordance with the characteristic curve IN indicated in FIG. 10, thereby outputting a voltage V14 representative of the result of comparison between input voltages V1 and V2.
The output voltage V14 is applied to inverter 3 shown in FIG. 9 and reversed, and then inverter 3 outputs an amplified output voltage V5. Therefore, this voltage comparator outputs, as an output voltage V5, a digital signal ("1" or "0") determined by the voltage values of the input voltage V1 and V2.
FIG. 11 is a sectional structural view of transistors 41, 47 and 53 which form CMOS analogue circuit 65 and CMOS digital circuit 66 shown in FIG. 8. As examples of transistors which form CMOS analogue circuit 65, NMOS transistor 41 and PMOS transistor 47 which form inverter 7 are shown. As an example of a transistor which form CMOS digital circuit 66, PMOS transistor 53 is shown. Assume that transistors 41, 47 and 53 shown in FIG. 11 are formed on an n-type semiconductor substrate 40. NMOS transistor 41 comprises: a p.sup.+ well region 42 formed in substrate 40; an n.sup.+ drain diffusion layer 43, an n.sup.+ source diffusion layer 44 and a P.sup.++ diffusion layer 45 each formed in well region 42; and a gate electrode 46 formed on the main surface of substrate 40 with an insulating film therebetween. Diffusion layer 45 is provided as a well contact of transistor 41.
PMOS transistor 47 comprises an n.sup.+ well region 48 formed in substrate 40, a p.sup.+ drain diffusion layer 49, a p.sup.+ source diffusion layer 50 and an n.sup.++ diffusion layer 51 each formed in well region 48; and a gate electrode 52. Diffusion layer 51 is provided as the well contact of transistor 47. Likewise, PMOS transistor 53 comprises an n.sup.+ well region 54 formed in substrate 40, a p.sup.+ drain diffusion layer 55, a p.sup.+ source diffusion layer 56 and a n.sup.++ diffusion layer 57 each formed in well region 54, and a gate electrode 58.
In a conventional LSI with an analogue circuit and a digital circuit provided on a single semiconductor substrate, it is pointed out that noise generated in the digital circuit is transmitted through the substrate to the analogue circuit, thereby causing erroneous operation by the analogue circuit. The change of voltage applied to drain diffusion layer 55 in transistor 53 shown in FIG. 11 is transmitted to substrate 40 through the junction capacitance between well region 54 and drain diffusion layer 55. The potential change transmitted to substrate 40 is delivered as noise to transistors 41 and 47 through substrate 40. Since NMOS transistor 41 is formed in p.sup.+ well region 42, it is not easily influenced by the noise. In contrast, as PMOS transistor 47 is formed in n.sup.+ well region 48 having the same conductivity type as that of substrate 40, i.e. the region with only the impurity concentration increased, the noise is transmitted into well region 48. Furthermore, the transmitted noise is also delivered to diffusion layer (well contact) 51, thereby causing the potential of well region 48 to drop. Therefore, the threshold voltage of transistor 47 is changed influenced by this noise, resulting in a change in the input-output characteristic of inverter 7 as shown by a broken line U in FIG. 13.
With reference to FIG. 12, more detailed description will be given in this connection. FIG. 12 shows the structure of PMOS transistor 47 of FIG. 11 in section more in detail. Noise N.sub.s is transmitted into n.sup.+ well region 48 through substrate 40. Of the transmitted noise N.sub.s, a part of the noise N1 is transmitted to well contact 51 through well region 48. Therefore, the resistance component Rw of well region 48 causes a potential drop in well region 48. As a result, due to a backgate effect, the absolute value of the threshold voltage of transistor 47 increases, thereby changing the transistor characteristic.
In addition, of the transmitted noise N.sub.s, the other part of the noise N2 is transmitted to drain diffusion layer 49 through the coupling capacitor formed between well region 48 and drain diffusion layer 49. Accordingly, the potential of drain diffusion layer 49 changes. Since drain diffusion layer 49 of transistor 47 constitutes the output of inverter 7, the potential change of drain diffusion layer 49 appears as the change in the output voltage of inverter 7. Accordingly, the input-output characteristic of inverter 7 changes in accordance with the curve U shown by a broken line in FIG. 13. Consequently, although an output voltage V14 should be obtained, which satisfies the relation in accordance with the following inequality (4), an output voltage V14 (value V.sub.c) to satisfy the relation in accordance with the following inequality (5) is output instead. EQU V14 (=V.sub.B)&gt;V0 (4) EQU V14 (=V.sub.c)&lt;V0 (5)
Therefore, influenced by the noise transmitted to PMOS transistor 47 which forms inverter 7 indicated in FIG. 9, inverter 7 will output the output voltage V14 representative of an erroneous result of comparison. That is, this voltage comparator will output an output signal V5 representative of an erroneous result of comparison between input voltages V1 and V2.
In the foregoing, the case was described in which the noise N.sub.s generated from CMOS digital circuit 66 adversely affects PMOS transistor 47. Now, generation of the noise N.sub.s in CMOS digital circuit 66 will be described below. FIG. 14 is a circuit diagram of a buffer circuit forming a part of CMOS digital circuit 66. The buffer circuit includes two cascaded CMOS inverters 31' and 32'. Each of inverters 31' and 32' is formed of a PMOS transistor and an NMOS transistor. Inverter 32', for example, includes a PMOS transistor 470 and an NMOS transistor 530 connected in series between the power supply V.sub.DD and ground. Each of inverters 31' and 32' has the same circuit configuration as that of inverter 7 and have the same input-output characteristic as the one shown in FIG. 10.
FIG. 15 is a cross sectional view showing the structure of transistors 470 and 530 forming inverter 32' shown in FIG. 14. Each of transistors 470 and 530 is formed in an n.sup.+ well region 480 and a p+ well region 540 each formed in an n type substrate. PMOS transistor 470 includes a p.sup.+ drain diffusion layer 490, a p.sup.+ source diffusion layer 500, and an n.sup.++ diffusion layer 51 formed in n.sup.+ well region 480, and a gate electrode 520 formed on substrate 40 through an insulating layer (not shown). NMOS transistor 530 includes an n.sup.+ drain diffusion layer 550, an n.sup.+ source diffusion layer 560, and a p.sup.+ diffusion layer formed in a p.sup.+ well region 540, and a gate electrode 580.
As NMOS transistor 530 is formed in p.sup.+ well region 540, a change in the voltage applied to n.sup.+ drain diffusion layer 550 is not easily transmitted as noise N.sub.s through substrate 40. A PMOS transistor 470 is, however, formed in n.sup.+ well region 480 having the same conductivity type as that of substrate 40, a change in the voltage applied to p.sup.+ drain diffusion layer 490 is liable to be transmitted to analogue circuit 65 as noise N.sub.s. through substrate 40. As shown in FIG. 12, NMOS transistor 47 in analogue circuit 65 is therefore subject to adverse effects due to the transmitted noise N.sub.s. It is pointed out that PMOS transistor in digital circuit 66 formed within n type substrate 40 is liable to generate the noise N.sub.s which can be easily transmitted through substrate 40.